Semiconductor integrated circuit and its reset method

ABSTRACT

In a circuit block  110  to be an object of power-off, voltage detecting circuits  130  and  134  are disposed near power supply terminals  140  and  142 , respectively, and voltage detecting circuits  132  and  136  are disposed at given positions far from the terminals  140  and  142 , respectively, on power lines  141  and  143  of two electric-supply systems. The voltage detecting circuits are each made of MOS transistors only. At turning on the power from a power supply circuit  150  again, after all the voltage detecting circuits have detected arrival of power-supply voltages at a predetermined potential, a reset signal generating circuit  160  stops the input of a reset signal to the circuit block  110.  Accordingly, since the reset state is stopped after the arrival of the power-supply voltages at the predetermined voltage, a semiconductor integrated circuit is initialized normally. This provides a semiconductor integrated circuit capable of generating a power-on reset signal appropriately.

TECHNICAL FIELD

[0001] The present invention relates to reduction of power consumptionin an LSI constituted by a plurality of circuit blocks and in a systemconstituted by a plurality of LSIs.

BACKGROUND ART

[0002] With recent progress of technology relating to LSIs, a pluralityof LSIs implementing sophisticated digital signal processing have beenincorporated into mobile equipment. Since the mobile equipment typifiedby cellular phones is driven by batteries, reduction of powerconsumption in the incorporating equipment by shutting off power supplyto an LSI which is not in operation has been widely performed for thepurpose of extending the operating time thereof. To bring the LSI to anoperating state again after the shut-off of the LSI, it is necessary toinitialize (reset) the LSI appropriately. In particular, the reset atturning on of power is called power-on reset.

[0003] To appropriately generate a signal for this power-on reset, theuse of a configuration in which a CR time constant circuit and aninverter are combined is known to date. Hereinafter, a conventionaltechnique will be described with reference to FIG. 12. A circuit shownin FIG. 12 is configured to generate a power-on reset signal 1220 froman inverter 1210 constituted by a p-MOS transistor 1215 and an n-MOStransistor 1217 when a potential 1203 at a CR time constant circuitconstituted by a resistor 1201 and a capacitance 1202 exceeds thethreshold voltage of the inverter 1210.

[0004] In addition to the configuration shown in FIG. 12, aconfiguration including a voltage divider circuit constituted by aresistance, a comparator, a time-constant circuit constituted by, forexample, a rated current generator and a capacitance, and an inverter isproposed as a power-on reset circuit in Japanese Laid-Open PublicationNo. 10-207580, for example.

[0005] (Problems to be Solved)

[0006] However, any of the conventional circuit configurations is formedby a resistor and a capacitor, so that the configurations are highlysusceptible to characteristic errors in the process of fabricating asemiconductor circuit. Accordingly, the conventional circuitconfiguration shown in FIG. 12 has a problem that a period during whicha reset signal is active changes from one product to another, and thusthe reset is stopped before the power-supply potential at an LSI or acircuit block to be reset (hereinafter, collectively referred to as “acircuit block”) rises to an appropriate value.

[0007] The configuration proposed in the above publication iscomplicated, so that there arises a problem that the configurationcannot be incorporated into an LSI easily.

DISCLOSURE OF INVENTION

[0008] It is therefore an object of the present invention to provide asemiconductor integrated circuit which does not generate a power-onreset signal until the power supply voltage in a circuit block to bereset rises to a predetermined potential and which is capable ofappropriately initializing the circuit block to which power is turned onagain.

[0009] To achieve this object, according to the present invention,attention is given to the fact that the potential on a power line variesdepending on positions on the power line, and thus potentials on thepower line are detected at a plurality of positions and all the resultsof these potential detections are considered, thereby generating apower-on reset signal.

[0010] Specifically, an inventive semiconductor integrated circuit ischaracterized by including: a circuit block including a power line of atleast one electric-supply system and a plurality of internalsemiconductor devices to which power is supplied from the power line;and a plurality of voltage detecting means each connected to the powerline at a given position on the power line and each outputting a voltagedetection signal at a given potential when the potential at the givenposition on the power line is a predetermined potential.

[0011] The inventive semiconductor integrated circuit is characterizedin that each of the plurality of voltage detecting means includesvoltage detecting means connected to the power line at a given positionon the power line farthest from a starting point of power supply.

[0012] The inventive semiconductor integrated circuit is characterizedin that: each of the plurality of voltage detecting means includes ap-MOS transistor and an n-MOS transistor; the power line is connected tothe drain of the p-MOS transistor; the gate of the p-MOS transistor andthe source and gate of the n-MOS transistor are grounded; and the sourceof the p-MOS transistor is connected to the drain of the n-MOStransistor at a connection point, and the potential at the connectionpoint is output as the voltage detection signal.

[0013] The inventive semiconductor integrated circuit is characterizedby including: first power supply means for supplying or shutting offpower to the circuit block in accordance with a power-supply controlsignal input from outside; reset signal generating means for inputtingthe voltage detection signals from the plurality of voltage detectingmeans and outputting a reset signal to the circuit block when all thevoltage detection signals from the plurality of voltage detecting meansare not at the given potential, while stopping the output of the resetsignal to the circuit block after all the voltage detection signals havereached the given potential; and second power supply means for supplyingpower to the reset signal generating means.

[0014] The inventive semiconductor integrated circuit is characterizedin that the reset signal generating means includes: a logic gate forreceiving the voltage detection signals from the plurality of voltagedetecting means and detecting that all the voltage detection signals areat the given potential; and a delay unit for delaying the output of thelogic gate by a given time, wherein the output of the delay unit isoutput to the circuit block as the reset signal.

[0015] The inventive semiconductor integrated circuit is characterizedin that the reset signal generating means includes: a logic gate forreceiving the voltage detection signals from the plurality of voltagedetecting means and detecting that all the voltage detection signals areat the given potential; and flip-flop circuits with a plurality ofstages for sequentially delaying the output of the logic gate with aclock signal input from outside; the output of the flip-flop circuit atthe final stage is output to the circuit block as the reset signal.

[0016] The inventive semiconductor integrated circuit is characterizedin that the first power supply means and the second power supply meansare integrated on a semiconductor substrate.

[0017] The inventive semiconductor integrated circuit is characterizedin that the circuit block and the reset signal generating means areintegrated on a semiconductor substrate.

[0018] The inventive semiconductor integrated circuit is characterizedin that the circuit block, the reset signal generating means, the firstpower supply means and the second power supply means are integrated on asemiconductor substrate.

[0019] A semiconductor-integrated-circuit-resetting method forresetting, to an initial state, a circuit block provided in asemiconductor integrated circuit including: a power line of at least oneelectric-supply system; and the circuit block including a plurality ofinternal semiconductor devices to which power is supplied from the powerline is characterized in that: power-supply potentials are detected at aplurality of positions on the power line; whether or not all thepower-supply potentials at the plurality of positions on the power linereach a predetermined potential is detected; and a reset signal to beoutput to the circuit block is stopped when the result of the detectionis true.

[0020] The inventive semiconductor-integrated-circuit-resetting methodis characterized in that: an inverter including a p-MOS transistor andan n-MOS transistor is provided; and the potentials on the power lineare detected using a potential detecting circuit in which the drain ofthe p-MOS transistor is connected to the power line.

[0021] As described above, according to the present invention, in theinside of the circuit block, though the power-supply potential decreasesas the distance from the starting point of power supply on the powerline increases, power-supply potentials are detected at a plurality ofpositions on the power line, so that the reset of the semiconductorintegrated circuit is stopped on or after the point in time when thedetected power-supply potentials reach a predetermined potential.Accordingly, the semiconductor integrated circuit is initializednormally, and then the semiconductor integrated circuit starts itsoperation.

[0022] In particular, according to the present invention, potentialdetecting means using neither a resistor nor a capacitor but using onlyMOS transistors generates a power-on reset signal, so that thesemiconductor integrated circuit is less susceptible to characteristicerrors in the process of fabrication, thus ensuring generation of thepower-on reset signal at a desired timing.

BRIEF DESCRIPTION OF DRAWINGS

[0023]FIG. 1 is a diagram showing an entire configuration of asemiconductor integrated circuit according to a first embodiment of thepresent invention.

[0024]FIG. 2 is a diagram showing an internal configuration of a voltagedetecting circuit provided in the semiconductor integrated circuit.

[0025]FIG. 3 is a graph showing a relationship between a rising edge ofa power supply voltage and a rising edge of a voltage detection signalat turning on power again.

[0026]FIG. 4 is a diagram showing an internal configuration of a resetsignal generating circuit provided in the semiconductor integratedcircuit.

[0027]FIG. 5 is a graph showing a relationship between rising edges of aplurality of voltage detection signals and the stopping of a resetsignal in the semiconductor integrated circuit.

[0028]FIG. 6 is a diagram showing an internal configuration of a resetsignal generating circuit provided in a semiconductor integrated circuitaccording to a second embodiment of the present invention.

[0029]FIG. 7 is a graph showing a relationship between rising edges of aplurality of voltage detection signals and the stopping of a resetsignal in the semiconductor integrated circuit.

[0030]FIG. 8 is a diagram showing an entire configuration of asemiconductor integrated circuit according to a third embodiment of thepresent invention.

[0031]FIG. 9 is a diagram showing an internal configuration of a resetsignal generating circuit provided in the semiconductor integratedcircuit.

[0032]FIG. 10 is a timing chart showing how the reset signal generatingcircuit operates.

[0033]FIG. 11 is a diagram showing an entire configuration of asemiconductor integrated circuit according to a fourth embodiment of thepresent invention.

[0034]FIG. 12 is a diagram showing a configuration of a conventionalcircuit for generating a power-on reset signal.

BEST MODE FOR CARRYING OUT THE INVENTION

[0035] Hereinafter, embodiments of the present invention will bedescribed with reference to the drawings.

[0036] (Embodiment 1)

[0037]FIGS. 1 through 5 show a semiconductor integrated circuitaccording to a first embodiment of the present invention.

[0038] In FIG. 1, reference numeral 110 denotes a circuit block, andreference numeral 150 denotes a first power supply circuit (first powersupply means) which supplies power to the circuit block 110 or shuts offthe supply. The first power supply circuit 150 receives a power-supplycontrol signal 155 and, when the power-supply control signal 155 isactivated, stops the power supply to the circuit block 110, thusreducing power consumption in the circuit block 110.

[0039] Reference numeral 160 denotes a reset signal generating circuit(reset signal generating means) which receives voltage detection signals131, 133, 135 and 137, which are output from the circuit block 110 andwill be described later, and supplies a reset signal 162 to the circuitblock 110 based on the voltage detection signals. Reference numeral 170denotes a second power supply circuit (second power supply means) whichsupplies power to the reset signal generating circuit 160 or shuts offthe supply.

[0040] The circuit block 110 has two power supply terminals 140 and 142which are connected to a power line 152 connected to the first powersupply circuit 150. The power supplied via the power supply terminals140 and 142 is supplied to a plurality of logic gates (semiconductordevices) 120, 122 and 124 constituted by MOS transistors incorporatedinto the circuit block 110 via a power line 141 of one electric-supplysystem, and is also supplied to a similar logic gate (semiconductordevice) 126 via a power line 143 of a different electric-supply systemfrom that of the power line 141. The number of logic gates incorporatedinto the circuit block 110 is four in FIG. 1, but a large number oflogic gates are incorporated therein in reality and several thousands toseveral tens of thousands of logic gates are normally incorporatedtherein.

[0041] In addition, voltage detecting circuits 130, 132, 134 and 136 arearranged near the power supply terminals 140 and 142, i.e., near thestarting points of power supply, and behind the logic gates 124 and 126farthest from the starting points of power supply. The four voltagedetecting circuits 130, 132, 134 and 136 in this arrangement areconnected to the power lines 141 and 143. In FIG. 1, the two voltagedetecting circuits 130 and 132 are connected to the power line 141whereas the two voltage detecting circuits 134 and 136 are connected tothe other power line 143. Each of the voltage detecting circuits 130,132, 134 and 136 detects the power-supply potential on the power line141 or 143 at the connection position thereof and, when the detectedpower-supply potential is at a predetermined value or more, outputs avoltage detection signal 131, 133, 135 or 137 at an H level (a givenlevel). The number of the voltage. detecting circuits 130, 132, 134 and136 incorporated in the circuit block 110 is two for each of the powerlines 141 and 143, i.e., is four in total. However, the presentinvention is not limited to this, and the voltage detecting circuits maybe provided in any number as long as the increase of the power-supplypotential on the power lines 141 and 143 is detected.

[0042] The circuit block 110 further includes a reset terminal 145 towhich a reset signal 162 from the reset signal generating circuit 160 isinput. Although not shown, when the potential of the input reset signal162 is at a Low level, the circuit block 110 initializes all theinternal states.

[0043] The voltage detecting circuits 130, 132, 134 and 136 have anidentical configuration. An internal configuration of the voltagedetecting circuit 130 will be described as an example based on FIG. 2.The voltage detecting circuit 130 shown in FIG. 2 includes an inverter135 in which a p-MOS transistor 130 a and an n-MOS transistor 130 b areconnected to each other. The power line 141 is connected to the drain ofthe p-MOS transistor 130 a. The gate of the p-MOS transistor 130 a andthe gate and source of the n-transistor 130 b are grounded (at a groundlevel). The source of the p-MOS transistor 130 a and the drain of then-MOS transistor 130 b are connected to each other, and the potential atthe connection point thereof is output as the voltage detection signal131. When the potential of power supplied from the power line 141increases to a value at which the p-MOS transistor 130 a starts itsoperation, the voltage detection signal 131, which is the sourcepotential of the p-MOS transistor 130 a, outputs a High level as shownin FIG. 3. In this case, the power-supply potential on the power line141 reaches a predetermined potential (hereinafter, referred to as Vdd)at time 310 in FIG. 3, and then the voltage detection signal 131 reachesthe High level (Vdd level). That is, the power line 141 has alreadyreached the predetermined potential Vdd before the voltage detectionsignal 131 reaches the High level.

[0044] The reset signal generating circuit 160 is configured by acircuit shown in FIG. 4. Specifically, the reset signal generatingcircuit 160 includes an AND gate 400 to which power is always suppliedfrom a second power supply circuit 170 through a power line 172. The ANDgate 400 receives the voltage detection signals 131, 133, 135 and 137from the four voltage detecting circuits 130, 132, 134 and 136 arrangedin the circuit block 110, and detects whether or not all the fourvoltage detection signals are at the High level, i.e., whether or notall the power-supply potentials at the connection points of therespective voltage detecting circuits 130, 132, 134 and 136 on the powerlines 141 and 143 are at the predetermined potential Vdd. If at leastone of the voltage detection signals is at a Low level (ground level),the AND gate 400 outputs a reset signal (Low level) 162. On the otherhand, if all the four voltage detection signals are at the High level(Vdd level) and the detection result is true, the AND gate 400 stops theoutput of the reset signal (Low level), while setting its output at theHigh level (Vdd level).

[0045] Now, operation of turning off and then on the power supplied fromthe power line 152 to the circuit block 110 will be described.

[0046] When the power-supply control signal 155 input from outside isactive, the first power supply circuit 150 outputs a High level(potential at Vdd) to the power line 152. When operation of the circuitblock 110 becomes unnecessary, the power-supply control signal 155 isdisabled. In this way, a potential at a Low level (ground level,i.e., 0V) is output to the power line 152. Since no power is supplied from thepower supply terminals 140 and 141 to the circuit block 110, all theoperations are stopped. At this time, power consumed in the circuitblock 110, i.e., power consumed by the MOS transistors forming the logicgates 120, 122, 124 and 126 incorporated into the circuit block 110, iszero. The voltage detection signals 131, 133, 135 and 137 output fromthe four voltage detecting circuits 130, 132, 134 and 136 at this timeis at the Low level as shown in FIG. 3. Accordingly, the reset signalgenerating circuit 160 outputs the reset signal 162 at the Low level.The circuit block 110 receives the reset signal 162 from the resetsignal generating circuit 160 via the reset terminal 145. Since thepotential input to the reset terminal 145 is at the Low level, theinside of the circuit block 110 is in a reset state.

[0047] To resume operation of the circuit block 110 in this state, thevoltage control signal 155 is activated first. Then, the first powersupply circuit 150 starts outputting a High level (potential at Vdd) tothe power line 152, and the circuit block 110 starts power supply fromthe power supply terminals 140 and 142 to the internal logic gates 120,122, 124 and 126 through the power lines 141 and 143. At this time, theperiod required for each of the potentials on the power lines 141 and143 to rise to the predetermined potential Vdd varies depending on thepositions because of the capacitances of the connected logic gates 120,. . . and the wiring capacitances of the power lines 141 and 143themselves. FIG. 5 shows an example of the state when the change of thevoltage detection signal 137 is the latest. In the reset signalgenerating circuit 160, all the voltage detection signals 131, 133, 135and 137 are at the High level at time 500 shown in FIG. 5, so that theAND gate 400 produces an output at a High level to start stopping theoutput of the reset signal 162 at the Low level. At this time, as hasbeen described with reference to FIG. 3, the power lines 141 and 143 inthe circuit block 110 have been already at the predetermined potentialVdd at all the positions including the farthest positions from therespective power supply terminals 140 and 142, and all the logic gates120, 122, 124 and 126 in the circuit block 110 have completedpreparations for operation. Thereafter, the stopping of the reset signal(Low level) 162 makes the circuit block 110 stop its reset state,thereby resuming operation.

[0048] In this manner, the circuit block 110 stops its reset state afterthe power-supply potential at every position on the internal power lines141 and 143 has reached the predetermined potential Vdd, so that thecircuit block 110 is always initialized normally and resumes itsoperation.

[0049] (Embodiment 2)

[0050] Now, a semiconductor integrated circuit according to a secondembodiment of the present invention will be described with reference toFIGS. 6 and 7. The entire configuration thereof is the same as thatshown in FIG. 1, and thus the description thereof will be omitted.

[0051] This embodiment is different from the first embodiment in thatthe configuration of the reset signal generating circuit 160 shown inFIG. 1 is replaced with a circuit configuration of a reset signalgenerating circuit 160′ shown in FIG. 6. Specifically, in the resetsignal generating circuit 160′ shown in FIG. 6, an AND gate (logic gate)600 detects that all the four voltage detection signals 131, 133, 135and 137 input thereto are at a High level (potential at Vdd), and uponthe detection, the AND gate 600 has its output potential transition froma Low level to a High level, thereby stopping the output of a resetsignal (Low level) 602. The output signal 602 at the High level is inputto a delay unit 610 in which three buffers are cascaded, is delayed by agiven time by the delay circuit 610, and then is output to the circuitblock 110.

[0052] Accordingly, as is clear from a timing chart shown in FIG. 7, thereset signal (Low level) 162 is stopped (reaches a High level) at apoint in time when a delay time produced by the delay circuit 610 haselapsed after time 500 at which the power-supply potential has reachedthe predetermined potential Vdd at every position on the power lines 141and 143 in the circuit block 110, i.e., at time 700, thus furtherensuring initialization of the circuit block 110, as compared to thefirst embodiment.

[0053] In this embodiment, the delay unit 610 in the reset signalgenerating circuit 160′ is formed by three buffers. Alternatively, anynumber of buffers may be provided as long as the reset signal is delayedby an appropriate time.

[0054] (Embodiment 3)

[0055] Now, a semiconductor integrated circuit according to a thirdembodiment of the present invention will be described with reference toFIGS. 8 through 10.

[0056] This embodiment is different from the first embodiment in that aclock signal 864 is input to a reset signal generating circuit 160″ fromoutside and that the reset signal generating circuit 160″ has aninternal configuration shown in FIG. 9.

[0057] Specifically, the reset signal generating circuit 160″ shown inFIG. 9 includes an AND gate (logic gate) 900, flip-flop circuits 910,920 and 930 with three stages and another AND gate 940. The AND gate 900detects that all the four voltage detection signals 131, 133, 135 and137 input thereto are at a High level (potential at Vdd). Upon thisdetection, the AND gate 900 outputs a High-level signal 902. TheHigh-level signal 902 stops the reset state of the flip-flop circuits910, 920 and 930 with three stages. The clock signal 864 is input toeach of the flip-flop circuits 910, 920 and 930.

[0058] The flip-flop circuit 910 at the first stage holds the High-levelsignal 902 from the AND gate 900 based on a rising edge of the clocksignal 864 and produces an output to the flip-flop circuit 920 at thesubsequent stage. The flip-flop circuit 930 at the second stage holdsthe output of the flip-flop circuit 910 at the first stage based on therising edge of the next cycle of the clock signal 864 and produces anoutput to the flip-flop circuit 930 at the third stage. In the samemanner, the flip-flop circuit 930 at the third stage (final stage) holdsthe output of the flip-flop circuit 920 at the second stage based on thenext rising edge of the clock signal 864. The other AND gate 940receives the respective outputs of the flip-flop circuits 910, 920 and930 with three stages and the High-level signal 902 from the AND gate900, and performs a logical AND operation, thereby outputting a resetsignal 162.

[0059] Accordingly, in this embodiment, as shown in FIG. 10, after thesignal 902 from the AND gate 900 has reached the High level (i.e., apower line in the circuit block 110 has reached a potential Vdd) at time1000, this High-level signal 902 is sequentially delayed and held by theflip-flop circuits 910, 920 and 930 based on every cycle of the clocksignal 864 at times 1010, 1020 and 1030, respectively. The reset stateof the circuit block 110 is not stopped until the three cycles of theclock signal 864 has passed so that the reset signal 162 reaches theHigh level. Accordingly, an appropriate reset signal is generated evenif the reset is stopped after a lapse of a given period of time as aspecification of the reset terminal 145 of the circuit block 110.

[0060] (Embodiment 4)

[0061] Now, a semiconductor integrated circuit according to a fourthembodiment of the present invention will be described with reference toFIG. 11.

[0062] In this embodiment, a circuit block 110 and a reset signalgenerating circuit 160 are formed and integrated on a singlesemiconductor substrate, thereby making a single-chip LSI 1100. Thiseliminates the necessity of controlling the power-on reset to thecircuit block 110 from the outside of the LSI 1100. Accordingly, poweris always supplied from a second power supply circuit 170 to a powerline 172, and it is sufficient that power is supplied from a power line152 connected to a first power supply circuit 150 only when the circuitblock 110 is operated. As a result, a system including the LSI 1100 iseasily constructed.

[0063] In this embodiment, the circuit block 110 and the reset signalgenerating circuit 160 are integrated on the single-chip LSI 1100.Alternatively, the first and second power supply circuits 150 and 170may be incorporated into the single-chip LSI 1100. Then, the number ofcomponents constituting the system can be reduced.

[0064] In the first through fourth embodiments, the circuit block 110has the power lines 141 and 143 of two electric-supply systems.Alternatively, the circuit block 110 may, of course, have oneelectric-supply system or three or more electric-supply systems. Thefirst and second power supply circuits 150 and 170 are configured forspecialized use for the circuit block 110 and the reset signalgenerating circuit 160, respectively. Alternatively, the first andsecond power supply circuits 150 and 170 may, of course, be a singlepower supply circuit commonly used for the circuits 110 and 160. In sucha case, it is sufficient for the common single power supply circuit tohave a configuration capable of controlling power supply to the circuitblock 110 via the power line 152 or shut-off of the supply.

1. A semiconductor integrated circuit, characterized by comprising: acircuit block including a power line of at least one electric-supplysystem and a plurality of internal semiconductor devices to which poweris supplied from the power line; and a plurality of voltage detectingmeans each connected to the power line at a given position on the powerline and each outputting a voltage detection signal at a given potentialwhen the potential at the given position on the power line is apredetermined potential.
 2. The semiconductor integrated circuit ofclaim 1, characterized in that each of the plurality of voltagedetecting means includes voltage detecting means connected to the powerline at a given position on the power line farthest from a startingpoint of power supply.
 3. The semiconductor integrated circuit of claim1, characterized in that: each of the plurality of voltage detectingmeans includes a p-MOS transistor and an n-MOS transistor; the powerline is connected to the drain of the p-MOS transistor; the gate of thep-MOS transistor and the source and gate of the n-MOS transistor aregrounded; and the source of the p-MOS transistor is connected to thedrain of the n-MOS transistor at a connection point, and the potentialat the connection point is output as the voltage detection signal. 4.The semiconductor integrated circuit of claim 1, characterized byincluding: first power supply means for supplying or shutting off powerto the circuit block in accordance with a power-supply control signalinput from outside; reset signal generating means for receiving thevoltage detection signals from the plurality of voltage detecting meansand outputting a reset signal to the circuit block when all the voltagedetection signals from the plurality of voltage detecting means are notat the given potential, while stopping the output of the reset signal tothe circuit block after all the voltage detection signals have reachedthe given potential; and second power supply means for supplying powerto the reset signal generating means.
 5. The semiconductor integratedcircuit of claim 4, characterized in that the reset signal generatingmeans includes: a logic gate for receiving the voltage detection signalsfrom the plurality of voltage detecting means and detecting that all thevoltage detection signals are at the given potential; and a delay unitfor delaying the output of the logic gate by a given time, wherein theoutput of the delay unit is output to the circuit block as the resetsignal.
 6. The semiconductor integrated circuit of claim 4,characterized in that the reset signal generating means includes: alogic gate for receiving the voltage detection signals from theplurality of voltage detecting means and detecting that all the voltagedetection signals are at the given potential; and flip-flop circuitswith a plurality of stages for sequentially delaying the output of thelogic gate with a clock signal input from outside; the output of theflip-flop circuit at the final stage is output to the circuit block asthe reset signal.
 7. The semiconductor integrated circuit of claim 4,characterized in that the first power supply means and the second powersupply means are integrated on a semiconductor substrate.
 8. Thesemiconductor integrated circuit of claim 4, characterized in that thecircuit block and the reset signal generating means are integrated on asemiconductor substrate.
 9. The semiconductor integrated circuit ofclaim 4, characterized in that the circuit block, the reset signalgenerating means, the first power supply means and the second powersupply means are integrated on a semiconductor substrate.
 10. Asemiconductor-integrated-circuit-resetting method for resetting, to aninitial state, a circuit block provided in a semiconductor integratedcircuit including: a power line of at least one electric-supply system;and the circuit block including a plurality of internal semiconductordevices to which power is supplied from the power line, the method beingcharacterized in that: power-supply potentials are detected at aplurality of positions on the power line; whether or not all thepower-supply potentials at the plurality of positions on the power linereach a predetermined potential is detected; and a reset signal to beoutput to the circuit block is stopped when the result of the detectionis true.
 11. The semiconductor-integrated-circuit-resetting method ofclaim 10, characterized in that: an inverter including a p-MOStransistor and an n-MOS transistor is provided; and the potentials onthe power line are detected using a potential detecting circuit in whichthe drain of the p-MOS transistor is connected to the power line.